Intel Confidential
CPD System Software Engineering (Mobility Group)
Intel® Graphics Media Accelerator
Video BIOS Release
Document
Production Version
15.4.3.64.1283
Microsoft Windows Vista* 64
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with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights
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Contact your local Intel sales office or
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* Other names and brands may be claimed as
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Copyright © Intel Corporation 2004-2007
This document contains information on products
in the design phase of development. The information herein is subject to change
without notice. Do not finalize a design with this information.
This document is organized into two
sections. Section A documents information only on PV and corresponding Hot Fix
releases. Section A is updated only when a PV release or a corresponding Hot
Fix Release is made. “PV Build” column reflects the build done by adding code
changes related to “Changes from Baseline Build (RCR#/DCN#)” to the build
indicated by “Baseline Build#”.
Section B documents information on
weekly Video BIOS builds. Build numbers in blue indicate
change in build from last week for a specific chipset.
A. Video BIOS PV and
Hot Fix Releases
|
PC
14.4 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
3394 7/16/2004 |
CopperRiver |
3359 |
DCN 318504 |
See details on DCN
below. |
|
|
1327 05/05/2006 |
915G |
3362 |
DCN
461491 DCN
459737 DCN
458542 DCN
435150 DCN
430314 DCN
436595 DCN
435196 DCN
435430 DCN
435416 DCN
433137 DCN
434634 DCN
433881 DCN
432586 BUG
1663413 / DCN 432755 BUG
1661039 / DCN 432456 BUG
1650139 / DCN 432416 BUG
1592361 / DCN 432017 BUG
1640106 / DCN 432042 DCN
432034 BUG 1655364 / DCN 431334 DCN 431069 DCN 430784 DCN 430573 DCN 429371 DCN 429898 DCN 426915 DCN 426335 DCN 426925 RCR 227931/ DCN 318291 RCR 281266 / DCN 381294 BUG
1257443 / DCN 318511 BUG 1429262 / DCN 319106 DCN 429332 DCN 427510 DCN 426925 BUG 1257443 / DCN 318511 BUG
1429262 / DCN 319106 DCN 426333 BUG 1603055, BUG 1603059 / DCN 425611 BUG 1591728, 1602995 / DCN 426372 DCN
424901 DCN
424688 DCN
424147 DCN
423889 DCN
424142 DCN 424128 RCR 289449
/ DCN 423889 DCN 322918 DCN 322890 DCN 319106 DCN 321755 DCN 320875 BUG 1257443 / DCN
318511 DCN 322130 RCR 289449 / DCN 322205 RCR 288519 / DCN 322853 |
See details for RCR/DCN below. |
|
|
PC 14.8 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
1411 12/14/2006 |
915GM (Alviso) |
3412 |
DCN 504556 DCN 504556 DCN 460377 DCN 461488 DCN 459738 DCN 460150 DCN 459768 DCN 458541 DCN 458107 DCN 457718 DCN 430315 DCN 458107 DCN 436593 DCN 436656 DCN 433390 DCN
433136 DCN
434633 DCN
433853 DCN
432585 BUG
1663413 / DCN 432757 BUG
1661098 / DCN 432479 BUG
1661039 / DCN 432449 BUG
1654828 / DCN 431356 BUG
1650139 / DCN 431356 BUG
1592361 / DCN 432019 BUG
1640106 / DCN 431379 DCN
430583 RCR
926507 / DCN 431489 BUG
1655364 / DCN 431335 BUG
1557554 / DCN 425242 DCN
431070 DCN
430781 BUG
1646938 / DCN 430782 DCN
427469 DCN
429618 DCN
429958 BUG 1638049 / DCN 429715 DCN 428993 DCN 429298 RCR 906257 / DCN 428231 BUG 1633536/DCN 428196 DCN 428197 BUG 1623036 / DCN 427942 BUG 1622125 / DCN 427894 DCN 427510 DCN 426425 DCN 427124 DCN 426335 DCN 426332 BUG 1602744 / DCN 425406 BUG 1603055, 1603059 / DCN 425455 BUG 1591728, 1602995 / DCN 426374 BUG
1598241 / DCN 425604 RCR
904115 / DCN 425927 DCN 423816 DCN 425143 DCN 424148 DCN 424150 RCR 289449 / DCN 423888 BUG 1565799 / DCN 432842 BUG 1572216 / DCN 423259 DCN 322919 DCN 322774 DCN 321756 DCN 321904 DCN 321904 RCR 289449 / DCN 322204 BUG 155912 / DCN 322854 RCR 288519 / DCN 322854 DCN 628492 |
See details for RCR/DCN below. |
|
|
PC
14.12 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
1374 08/25/2006 |
945G
(Lakeport) |
1217 |
DCN 483767 DCN 483767 DCN 461352 DCN 459739 DCN 458540 DCN 430363 DCN 430314 DCN 436594 DCN 436265 DCN 435415 DCN 433135 DCN 434632 DCN 433852 DCN
432587 BUG
1663413 / DCN 432754 BUG
1661039 / DCN 432435 BUG
1650139 / DCN 432415 BUG
1592361 / DCN 432020 BUG
1640106 / DCN 432040 DCN
432035 BUG
1655364 / DCN 431424 DCN
431071 DCN
430572 DCN
429615 DCN
429957 DCN
429609 BUG
1638049 / DCN 429715 DCN
429297 DCN
428332 DCN
428197 |
See
details for RCR/DCN below. |
|
|
PC
14.18 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
1471 03/23/2007 |
945GM
(Calistoga) |
1256 |
DCN 516804 DCN 516293 DCN 515911 DCN 505438 DCN 515899 DCN 504533 DCN 504673 DCN 483767 DCN 482904 DCN 460487 DCN 459794 DCN 460832 DCN 460334 DCN 459063 DCN 460196 DCN 459743 DCN 460159 DCN 459505 DCN 459310 DCN 457779 DCN 458105 DCN 457719 DCN 458109 DCN 430301 DCN 458105 DCN 436592 DCN 436621 DCN 436265 DCN
435414 DCN
628062 DCN
983189 DCN
628322 DCN
628919 DCN
629989 DCN
628495 DCN
630565 DCN
631252 DCN
631644 DCN
631475 DCN
631796 |
See
details for RCR/DCN below. |
|
|
PC
14.21 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
1471 03/23/2007 |
Q965/Q963/G965
(Broadwater) |
1348 |
DCN 516804 DCN 516293 DCN 515899 DCN 505143 DCN 504673 DCN 504497 DCN 494381 DCN 628062 DCN 628062 DCN
628919 DCN
628996 DCN
628992 DCN
628682 DCN
630565 DCN
631252 DCN
631644 DCN
631796 DCN
631697 |
See
details for RCR/DCN below. |
|
|
PC
14.27 |
PV
Build & Date |
Chipset |
Baseline
Build # |
Changes
from Baseline Build (RCR#/DCN#) |
Notes |
|
1471 03/23/2007 |
GM965/PM985/GL960
(Crestline) |
1436 |
DCN
630565 DCN
631252 DCN
631644 DCN 631475 DCN
631796 |
See
details for RCR/DCN below. |
|
Latest
Video BIOS Builds Since: 03/23/2007 |
|
|
Build # |
Chipset Family |
|
1471 |
Bearlake-G |
|
1471 |
GM965/PM985/GL960 |
|
1471 |
G965/Q963/Q965 |
|
1471 |
945GM |
|
1374 |
945G |
|
1411 |
915GM (Alviso) |
|
3394 |
|
|
1327 |
915G (Grantsdale) |
|
1252 |
865G ( |
|
1270 |
855GM (MGM) |
|
3364 |
845G (Brookdale) |
|
3361 |
830M |
B. Video BIOS Weekly Builds
|
Video BIOS Release Note: 03/23/2007 |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
Build |
|
97266 |
2326402 |
N/A |
631697 |
Fixed blank display issue on
SDVO CRT |
G965 |
1471 |
|
98190 |
2335279 |
N/A |
631796 |
Fixed incorrect vertical
frequency issue when EFP display device attached to the system after POST. |
945GM G965 GM965 BLB |
1471 |
|
98547 |
631475 |
N/A |
631475 |
Fixed
issue that output Hsync and Vsync
polarities are unchanged after users modifying the polarities using BMP |
945GM GM965 |
1466 |
|
99677 |
2333398 |
N/A |
631644 |
Fixed DVI display goes blank when HDD
password enabled. In restore function, disable
pipe/dpll before restoring the clock and DPLL
registers. |
945GM Q965 GM965 BLB |
1466 |
|
N/A |
N/A |
992509 |
631252 |
Reverse the definition for new VBT
“Enable Internal Source Termination for HDMI” bit to meet the requirement
from the customer (0 =
External Termination 1 = Internal Termination). |
945GM Q965 GM965 BLB |
1459 |
|
NA |
NA |
995144 |
631046 |
Turn off unused Pipe/DPLL for desktop
VBIOS from Brearlake-G and later. |
BLB |
1455 |
|
NA |
NA |
992509 |
630565 |
Added a VBT bit to determine Internal or
External source termination for HDMI |
BLB |
1447 |
|
NA |
NA |
992509 |
630565 |
1-
Removed DFGT(Dual Frequency Graphics Technology) feature in VBT 2- Implemented new (BUN #07ww06) to
disable HPLL before updating the backlight control (LBPC) register. 3- Added a VBT bit to determine
Internal or External source termination for HDMI |
GM965 |
1447 |
|
NA |
NA |
992509 |
630565 |
Added a VBT bit to determine Internal
or External source termination for HDMI |
Q965 |
1447 |
|
NA |
NA |
992509 |
630565 |
Added a VBT bit to determine Internal
or External source termination for HDMI |
945GM |
1447 |
|
NA |
NA |
NA |
628495 |
Fixed
the BSF script file for SDVO port motherboard down solution on SDVO device 2. |
BLB |
1436 |
|
NA |
NA |
NA |
628495 |
Fixed the
BSF script file for SDVO port motherboard down solution on SDVO device 2. |
GM965 |
1436 |
|
NA |
NA |
NA |
628495 |
Fixed
the BSF script file for SDVO port motherboard down solution on SDVO device 2. |
Q965 |
1436 |
|
NA |
NA |
NA |
628495 |
Fixed the
BSF script file for SDVO port motherboard down solution on SDVO device 2. |
945GM |
1436 |
|
97552 97876 97928 97930 98005 |
2290780 |
NA |
629638 629106 629989 |
1- Fixed
Boot screen issue when Panel Fitting turned off in CMOS setup. 2- Fixed
TV boot issue on GM965/PM985/GL960 C) 3- Fixed
wrong PnP DID VBT value for LVDS Panel 1280x800 4- Fixed
issue that POST Message and Windows Log appear on Top-Left corner of SDVO
LVDS 5- Fixed
the compatibility issue on the new implementation that SSC option for each
individual panel. |
GM965 |
1435 |
|
94969 |
2222851 |
NA |
629106 |
1- Fixed
issue that POST Message and Windows Log appear on Top-Left corner of SDVO
LVDS |
Q965 |
1435 |
|
98284 |
2293163 |
NA |
629989 |
1- Fixed
the compatibility issue on the new implementation that SSC option for each
individual panel. |
945GM |
1435 |
|
NA |
2223286 |
NA |
628919 628996 628992 |
1-
Re-architect the EFP (including HDMI) EDID parsing 2- Update
the HDMI display checking function by reading CEA Vendor Specific 3- Matched the code with latest DPLL
algorithm for 8-bit DAC support |
BLB |
1428 |
|
NA |
2222851 2223286 |
988097 |
628919 628996 628992 |
1- Re-architect
the EFP (including HDMI) EDID parsing 2-
Update the HDMI display checking function by reading CEA Vendor Specific 3-
Matched the code with latest DPLL algorithm for 8-bit DAC support 4- Fixed issue that POST message and
Windows Logo appearing on Top Left of the Screen with CRT display 5- Added
a new Aspect Ratio option for VBIOS that is independent of the driver |
GM965 |
1428 |
|
NA |
2222851 2223286 |
NA |
628919 628996 628992 628682 |
1- Re-architect
the EFP (including HDMI) EDID parsing 2-
Update the HDMI display checking function by reading CEA Vendor Specific 3- Matched the code with latest DPLL
algorithm for 8-bit DAC support 4- Fixed issue that POST message and
Windows Logo appearing on Top Left of the Screen with CRT display |
Q965 |
1428 |
|
NA |
2223286 |
NA |
628919 |
Re-architect
the EFP (including HDMI) EDID parsing Update
the HDMI display checking function by reading CEA Vendor Specific |
945GM |
1428 |
|
NA |
NA |
NA |
628919 |
Apply
720p on HDMI for both VGA modes and VESA 101h timing |
945GM |
1413 |
|
88764 |
2053094 |
N/A |
628492 |
Fixed hang issue with
protected mode interface. |
915GM |
1411 |
|
NA |
NA |
988097 |
628682 |
1- Separated Aspect Ratio VBT bit with the driver Driver feature. 2- Fixed issue TV doesn’t turn on TV detection is done. 3- Changed default VBT value for TV hot plug to disable. 4- Fixed Cursor corruption issue after S3 resume. |
GM965/PM985/GL960 |
1410 |
|
NA |
NA |
NA |
628466 |
Description: Added the support for the latest the
Bearlake-G DPLL spreadsheet for 8-bit DAC |
Bearlake-G |
1402 |
|
88709 |
2040279 |
NA |
628322 |
Description: 1. System hung-up when going back to WinXP graphics platform after setting VESA mode under debug.exe
utility from FSDOS. Solution: Added Ring Buffer disabling code before
restoring Ring Buffer registers to fix the error in Ring Buffer registers
restore routine. |
Bearlake-G |
1402 |
|
NA |
NA |
NA |
628610 |
Description Fixed cursor
corruption when pop-up enabled on XP Solution Added
code to specify pop-up on VGA or Highres |
GM965/PM985/GL960 |
1402 |
|
94344 |
2222429 |
NA |
628610 |
Description LFP
screen does not turn off while running PC14_BCO.exe application Solution: VBIOS
updated VGA plane blank display to avoid the LFP screen off problem |
GM965/PM985/GL960 |
1402 |
|
94320 95542 |
2223814 |
NA |
628610 |
Description VESA
power management function doesn’t turn on TV when power off to on Solution SW workaround
by toggling the pipe access before enabling TVout |
GM965/PM985/GL960 |
1402 |
|
94992 95355 95456 96592 |
2210964 |
NA |
628628 |
Description Backlight
control hotkey works invert use customer’s normal polarity inverter Solution: Change the
PWM2 register polarity bit for always active high for both invert/normal
polarity inverter. |
GM965/PM985/GL960 |
1402 |
|
88709 |
2040279 |
NA |
628322 |
Description: 1. System hung-up when going back to WinXP graphics platform after setting VESA mode under
debug.exe utility from FSDOS. Solution: Added Ring Buffer disabling code before
restoring Ring Buffer registers to fix the error in Ring Buffer registers
restore routine. |
GM965/PM985/GL960 |
1402 |
|
88709 |
2040279 |
NA |
628322 |
Description: 1. System hung-up when
going back to WinXP graphics platform after setting
VESA mode under debug.exe utility from FSDOS. 2. Workaround hang issue
with JVC Panel Solution: 1. Added Ring Buffer disabling code before
restoring Ring Buffer registers to fix the error in Ring Buffer registers
restore routine. 2. Force to VBIOS to support
640x480@60Hz not matter what EDID indicates about this timing |
G965/Q963/Q965 |
1402 |
|
88709 |
2040279 |
NA |
628322 |
Description: 1. System hung-up when going back to WinXP graphics platform after setting VESA mode under
debug.exe utility from FSDOS. Solution: Added Ring Buffer disabling code before restoring
Ring Buffer registers to fix the error in Ring Buffer registers restore
routine. |
945GM |
1402 |
|
NA |
NA |
991006 |
983198 |
Description: 1. The new
feature can be enabled by the VBT bit.
If the feature enabled, VBIOS shall use 1280x720@60Hz for VGA
centering if HDMI display support this timing; otherwise, preferred timing
shall be used. |
945GM |
1398 |
|
306529 |
2196825 |
NA |
628062 |
Description: 1. Fixed ACPI
hotkey display change doesn’t work when EFP device hot-plugged. 2. Added
pop-up support for GM965/PM985/GL960. 3. Fixed VGA mode failure when using 1080i
capability TV 4. Initialize memory model to linear memory during setmode Solution: 1. Fixed the algorithm of the next display combo so
it will skip the VBIOS mode qualification when EFP is hot plugged. 2. The feature was added for GM965/PM985/GL960. 3. Decreased the TV throttling value during VBIOS
POST. 4. Initialize memory model to linear memory during setmode instead of using default memory mode. |
GM965/PM985/GL960 |
1393 |
|
306529 |
2196825 |
NA |
628062 |
Description: 1. Initialize memory model to linear memory during setmode Solution: 1. Initialize memory model to linear memory during setmode instead of using default memory mode. |
G965/Q963/Q965 |
1393 |
|
306529 |
2196825 |
NA |
628062 |
Description: 1. Fixed
ACPI hotkey display change doesn’t work when EFP device hot-plugged. Solution: 1. Fixed the algorithm of the next display combo so
it will skip the VBIOS mode qualification when EFP is hot plugged. |
945GM |
1393 |
|
N/A |
N/A |
N/A |
N/A |
Pre-Alpha
Release |
Bearlake-G |
1385 |
|
N/A |
N/A |
N/A |
516782 |
Description: Power-on
defaults for TV Contrast and Saturation result in background color display
corruption. Solution: The
power-on defaults for TV contrast and saturation have been updated from 945GM
to GM965/PM985/GL960. Video BIOS has updated the defaults for TV
Initialization. |
GM965/PM985/GL960 |
1382 |
|
92357 |
2142237 |
N/A |
516293 |
Description: The
signal output from the SDVO-HDMI card when connected to a HDMI display is not
shown as a HDMI signal when connected to a HDMI analyzer. This is because the
AVI InfoFrames are not being transmitted. Solution: Support
for the transmission of AVI InfoFrames has been
added for SDVO-HDMI. |
GM965/PM985/GL960 |
1377 |
|
N/A |
N/A |
N/A |
516804 |
Description: Support
for a dynamic IOBAR has been removed due to the condition of illegal PCI
device accesses during Windows operation. |
GM965/PM985/GL960 |
1377 |
|
93786 93969 |
2159176 |
N/A |
516804 |
Description: Change vga mode support model for EFP. 945GM graphics supports
centering in vga modes, so the vga
modes will be centered in the 640x480 timing. Since G965/Q963/Q965 /
GM965/PM985/GL960 graphics engine does not support vga
centering, the scalar will be used in vga modes for
these chipsets. |
GM965/PM985/GL960 |
1377 |
|
N/A |
N/A |
N/A |
516103 |
Description: The Tiano BIOS boot up screen is corrupted when using a
Silicon Image 1390 ADD2 card with HDMI monitor. The monitor does NOT support
the standard VESA timing for 800x600@60Hz which is being used by default. Solution: Update
the timing selection algorithm to consider the support for this mode and if
not supported, then use the preferred timings from the EDID. |
GM965/PM985/GL960 |
1377 |
|
N/A |
N/A |
N/A |
516106 |
Description: This
update will remove the necessary workarounds for the A0 silicon stepping.
This will support both A0 and B0 silicon steppings.
|
GM965/PM985/GL960 |
1377 |
|
92357 |
2142237 |
N/A |
516293 |
Description: The signal
output from the SDVO-HDMI card when connected to a HDMI display is not shown
as a HDMI signal when connected to a HDMI analyzer. This is because the AVI InfoFrames are not being transmitted. Solution: Support
for the transmission of AVI InfoFrames has been
added for SDVO-HDMI. |
G965/Q963/Q965 |
1377 |
|
93786 93969 |
2159176 |
N/A |
516804 |
Description: Change vga mode support model for EFP. 945GM graphics supports
centering in vga modes, so the vga
modes will be centered in the 640x480 timing. Since G965/Q963/Q965 /
GM965/PM985/GL960 graphics engine does not support vga
centering, the scalar will be used in vga modes for
these chipsets. |
G965/Q963/Q965 |
1377 |
|
N/A |
N/A |
N/A |
516804 |
Description: Support
for a dynamic IOBAR has been removed due to the condition of illegal PCI
device accesses during Windows operation. |
G965/Q963/Q965 |
1377 |
|
92357 |
2142237 |
N/A |
516293 |
Description: The signal
output from the SDVO-HDMI card when connected to a HDMI display is not shown
as a HDMI signal when connected to a HDMI analyzer. This is because the AVI InfoFrames are not being transmitted. Solution: Support
for the transmission of AVI InfoFrames has been
added for SDVO-HDMI. |
945GM |
1377 |
|
93786 93969 |
2159176 |
N/A |
516804 |
Description: Change vga mode support model for EFP. 945GM graphics supports
centering in vga modes, so the vga
modes will be centered in the 640x480 timing. Since G965/Q963/Q965 /
GM965/PM985/GL960 graphics engine does not support vga
centering, the scalar will be used in vga modes for
these chipsets. |
945GM |
1377 |
|
N/A |
N/A |
N/A |
516804 |
Description: Support
for a dynamic IOBAR has been removed due to the condition of illegal PCI
device accesses during Windows operation. |
945GM |
1377 |
|
N/A |
N/A |
N/A |
N/A |
Description: The VBT Version number has been increased due to the
incorrect build for 1358. This has been updated for the driver. |
915GM |
1377 |
|
90007 |
2138735 |
N/A |
515911 |
Description: ACPI hot key for display toggling
doesn’t continue loop after TV device is removed from VBT display configuration
removal table. The root cause is that VBIOS Get Next Display Device function
did not check the VBT display configuration removal table while running in WinXP. Solution: |
GM965/PM985/GL960 |
1374 |
|
92357 |
2142237 |
N/A |
515899 |
Description: Video
BIOS is not reading the correct bit for Audio Support in the EDID in determining
HDMI support by the display device. This issue does not occur on all displays
due to different EDIDs; since the incorrect bit was
read for this support. Solution: Update
the Audio Support check with the correct bit. |
GM965/PM985/GL960 |
1374 |
|
N/A |
2125523 |
N/A |
504962 |
Description: 1. When enabled the “preserve aspect ratio” bit in VBT,
LFP screen disappeared. 2. Gen 4 does not support text centering mode. However
ACPI hotkey could change text centering mode Solution: 1. After calculate the display and panel ratio, it
change the scaling mode to auto-scale, Pillarbox
and Letterbox. 2. Disabled
the Gen4 text centering mode |
GM965/PM985/GL960 |
1374 |
|
92357 |
2142237 |
N/A |
515899 |
Description: Video
BIOS is not reading the correct bit for Audio Support in the EDID in
determining HDMI support by the display device. This issue does not occur on
all displays due to different EDIDs; since the
incorrect bit was read for this support. Solution: Update
the Audio Support check with the correct bit. |
G965/Q963/Q965 |
1374 |
|
90007 |
2138735 |
N/A |
515911 |
Description: ACPI hot key for display toggling
doesn’t continue loop after TV device is removed from VBT display configuration
removal table. The root cause is that VBIOS Get Next Display Device function
did not check the VBT display configuration removal table while running in WinXP. Solution: |
945GM |
1374 |
|
90720 |
2126206 |
N/A |
505438 |
Description: Some
customer systems boot with a blank LVDS panel. This is caused by a false CRT detection
when no CRT is attached. This issue does NOT occur on the CRB. Solution: With the
|
945GM |
1374 |
|
92357 |
2142237 |
N/A |
515899 |
Description: Video
BIOS is not reading the correct bit for Audio Support in the EDID in
determining HDMI support by the display device. This issue does not occur on
all displays due to different EDIDs; since the
incorrect bit was read for this support. Solution: Update
the Audio Support check with the correct bit. |
945GM |
1374 |
|
N/A |
N/A |
N/A |
483767 |
Description: A New
implementation for providing the VBIOS version number for VISTA O/S is needed
by the Graphics Driver. Solution: VBIOS
added the VBIOS version echo data in VBT. Note: the VBIOS version echo
will only work with a Graphics Driver supporting this new implementation. |
945G |
1374 Update from 1358 Build. See
1358 notes for details. |
|
N/A |
N/A |
957123 |
504556 |
Description: Requested Spread Spectrum Control assignment for
each panel profile. Solution: Updated the VBT to support Spread Spectrum Control
for each panel profile. |
915GM |
1374 Update from 1358 Build. See
1358 notes for details. |
|
88582 |
2039278 |
N/A |
505143 |
Description: With dual core in the particular
scenario W2K video port is calling driver to set hi-res mode and concurrently
issues int10 to VBIOS to set FSDOS. This results in driver and VBIOS
accessing GMCH simultaneously causing issues. Solution : To fix the problem a SW flag in MMIO
7041Ch was defined to synchronize mode set for driver and VBIOS. |
G965/Q963/Q965 |
1371 |
|
N/A |
N/A |
980395 |
504653 |
Description : An RCR requested the capability to configure each Integrated
LVDS panel profile for either 18bpp or 24bpp. Solution : Updated the VBT to
support a 18/24 bpp selection for each Integrated LVDS panel profile. |
GM965/PM985/GL960 |
1368 |
|
N/A |
N/A |
929544 |
504533 |
Description: Requested TV hotplug Enable/Disable bit Solution: Added the VBT to
select TV hotplug Enable/Disalbe |
945GM |
1362 |
|
N/A |
N/A |
929544 |
504533 |
Description: Requested TV hotplug Enable/Disable bit Solution: Added the VBT to
select TV hotplug Enable/Disable bit. |
GM965/PM985/GL960 |
1362 |
|
N/A |
N/A |
929544 |
504533 |
Description: Hi-resolution
border needs to be disabled when TVout or Panel
Fitter2 is enabled. Solution: Removed the
hi-resolution mode border when TVout or Panel
Fitter2 is enabled. |
GM965/PM985/GL960 |
1362 |
|
90969 |
N/A |
N/A |
504673 |
Description: CRT
display using a Ch7021 ADD2 card results in an incorrect refresh rate for VGA modes 0+/1+/2+/3+ (71Hz, should be 70Hz)
and VESA modes with resolution of 640x480 (63Hz, should be 60Hz). The
VBIOS was programming the wrong 60Hz timing table for a 720x400 resolution
mode, resulting in the incorrect timings for some VGA modes. The CH-7021
encoder does not support a border in the timings, so the 640x480 VESA modes
were not being programmed correctly in this regard. Solution: To fix
VGA mode problem we need to use the IBM VGA 70Hz timing table. To fix the
problem for VESA 640x480 mode we need to replace the timing table with the
one that is no display boarder. |
GM965/PM985/GL960 |
1362 |
|
90969 |
N/A |
N/A |
504673 |
Description: CRT
display using a Ch7021 ADD2 card results in an incorrect refresh rate for VGA modes 0+/1+/2+/3+ (71Hz, should be 70Hz)
and VESA modes with resolution of 640x480 (63Hz, should be 60Hz). The
VBIOS was programming the wrong 60Hz timing table for a 720x400 resolution
mode, resulting in the incorrect timings for some VGA modes. The CH-7021
encoder does not support a border in the timings, so the 640x480 VESA modes
were not being programmed correctly in this regard. Solution: To fix
VGA mode problem we need to use the IBM VGA 70Hz timing table. To fix the
problem for VESA 640x480 mode we need to replace the timing table with the
one that is no display boarder. |
G965/Q963/Q965 |
1362 |
|
90969 |
N/A |
N/A |
504673 |
Description: CRT
display using a Ch7021 ADD2 card results in an incorrect refresh rate for VGA modes 0+/1+/2+/3+ (71Hz, should be 70Hz)
and VESA modes with resolution of 640x480 (63Hz, should be 60Hz). The
VBIOS was programming the wrong 60Hz timing table for a 720x400 resolution
mode, resulting in the incorrect timings for some VGA modes. The CH-7021
encoder does not support a border in the timings, so the 640x480 VESA modes
were not being programmed correctly in this regard. Solution: To fix
VGA mode problem we need to use the IBM VGA 70Hz timing table. To fix the
problem for VESA 640x480 mode we need to replace the timing table with the
one that is no display boarder. |
945GM |
1362 |
|
Video
BIOS Build Date: 07/14/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1358 |
G965/Q963/Q965 |
|||||
|
1358 |
GM965/PM985/GL960 |
|||||
|
1358 |
945G |
|||||
|
1358 |
945GM |
|||||
|
1358 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
2076605 |
957123 |
483767 504585 |
Description:
Solution: 1. Updated the VBT to support Spread
Spectrum Control for each panel profile. 2. VBIOS disables clock gating before
changing the PWM2 resister. 3. Removed the Gen3 algorithm of
pipe-support. From Gen4 and later, both Pipes (A/B) are capable of using the
assignable scalar in dual clone mode. The algorithm for Dual-Display Clone
has been updated in regards to assigning the scalar. |
GM965/PM985/GL960 |
|
|
90967 90969 90973 HSD
#300079 |
2053136 2077511 |
N/A |
504497 |
Description: Video BIOS is currently setting HSync
and VSync polarities for the Solution: Video BIOS
initializes the Sync Polarities of the SDVO Ports to positive (default.) |
G965/Q963/Q965 GM965/PM985/GL960 |
|
|
N/A |
N/A |
957123 |
483767 |
Description: 1
Requested Spread Spectrum Control assignment for each panel profile. 2
A New implementation for
providing the VBIOS version number for VISTA O/S is needed by the Graphics
Driver. Solution: 1
Updated the VBT to support Spread Spectrum Control for each panel profile. 2
VBIOS added the VBIOS
version echo data in VBT. Note: the VBIOS version echo will only
work with a Graphics Driver supporting this new implementation. |
945GM |
|
|
N/A |
N/A |
N/A |
483767 |
Description: A New implementation for providing
the VBIOS version number for VISTA O/S is needed by the Graphics Driver. Solution: VBIOS added the VBIOS version
echo data in VBT. Note: the VBIOS version echo will only
work with a Graphics Driver supporting this new implementation. |
945G DO NOT USE THIS VERSION: |
|
|
N/A |
N/A |
957123 |
504556 |
Description: Requested
Spread Spectrum Control assignment for each panel profile. Solution: Updated
the VBT to support Spread Spectrum Control for each panel profile. |
915GM DO NOT USE THIS VERSION: |
|
|
Video
BIOS Build Date: 06/30/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1354 |
G965/Q963/Q965 |
|||||
|
1348 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1343 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
N/A |
#494381 |
Description: The code update
in build 1339 should have only been applied for GM965/PM985/GL960 only. This
removes the change for G965/Q963/Q965 to avoid potential issues. |
G965/Q963/Q965 |
|
|
Video
BIOS Build Date: 06/22/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1348 |
G965/Q963/Q965 |
|||||
|
1348 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1343 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
HSD#576274 HSD#306017 HSD#306136 HSD#306083 HSD#576120 |
N/A |
N/A |
#483495 #483691 #483538 #483804 |
Description: 1.
TV doesn’t boot-up connect sVideo TV cable when select VBT default. 2. VBIOS must program PWM2 and Panel Power
Control registers. 3. Backlight Control register does not work
when set to FFh. 4. Si workaround needed for Clock Gating
Disable for Rendering Register. Solution: 1.
Added workaround for
S-Video detection. 2.
Program PWM2, Panel Power
Control and Clock Gating Disable for
Render registers during VBIOS POST. 3.
Added a workaround to avoid
an writes to the Backlight Control register for a configuration of FFh. |
G965/Q963/Q965 GM965/PM985/GL960 |
|
|
Video
BIOS Build Date: 06/09/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1345 |
G965/Q963/Q965 |
|||||
|
1345 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1343 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
HSD
306097 |
N/A |
N/A |
483146 |
Description: 1. A silicon bug promotes a system hang after MI_FLUSH in the game
“Beyond Good & Evil.” One
workaround had been added to fix same issue for G965/Q963/Q965 starting from
VBIOS release 1329, but that workaround was not enabled for
GM965/PM985/GL960. To workaround the problem, a new "MT Constant Read Bug Fix
Disable Chicken Bit" is defined in Cache Mode Register 0. This new bit
must be set to "0" during Video POST. 2.
The
workaround
code for ADD2 card detection for A0 silicon needs to be cleared up for
G965/Q963/Q965 C0 and later silicon. Solution: 1. Enable the workaround for GM965/PM985/GL960. 2.
Remove
the workaround for ADD2 card detection for G965/Q963/Q965 A0. |
GM965/PM985/GL960 G965/Q963/Q965 |
|
|
Video
BIOS Build Date: 06/07/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1339 |
G965/Q963/Q965 |
|||||
|
1339 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1343 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
87134 |
1998417 |
N/A |
482904 |
Description In dual display clone or extended
desktop modes (where one display is LVDS), the use of the panel-fitting
hot-key results in loss of display or corruption for the non-LVDS display.
Video BIOS is overriding both pipes during the panel-fitting operation. Solution: Since LVDS is only present on one
pipe, Video BIOS will override that pipe only during the execution of panel-fitting.
|
945GM |
|
|
Video
BIOS Build Date: 05/18/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1339 |
G965/Q963/Q965 |
|||||
|
1339 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1334 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
88870 88871 88819 HSD
306048 |
N/A |
N/A |
482907 |
Description 1.
CRT off after a device
switch from TV to CRT. 2.
LFP screen off when mode
changes from hi-res to VGA. 3.
VGA mode doesn’t work on
LVDS the first time after a display switch to LVDS. 4.
MDK DOS game doesn’t work
on LVDS display. Note: All of these are
root-caused to a change implemented in 1327, which was not implemented fully:
checking for the VGA plane to be off after the pipe is disabled, but before
checking pipe (on/off) status. Solution: Inserted this sequence in the
last location where this needed to be implemented. |
G965/Q963/Q965 GM965/PM985/GL960 |
|
|
Video
BIOS Build Date: 05/18/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1334 |
G965/Q963/Q965 |
|||||
|
1334 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1334 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
N/A |
472326 |
Description: Panel fitting is not turned on in mode 3 for SDVO LVDS when
display switches to LFP with pipe B. Root Cause: Pipe scalar assignment algorithm was limited to handle internal
LVDS only; it did not handle SDVO LVDS. The panel fitting flag was not set
correctly for pipe B. Solution: Turned on pipe scalar assignment algorithm for SDVO LVDS. |
G965/Q963/Q965 GM965/PM985/GL960 |
|
|
545692 |
2001697 |
N/A |
461505 |
Description: Parallel to Serial Load Pulse phase selection defined in DPLL
A/B control registers was not initialized base on BSpec
requirement with the correct value. Solution: Set the correct default value for DPLL Reference Clock |
G965/Q963/Q965 |
|
|
N/A |
N/A |
N/A |
460487 |
Description: Video BIOS previously initialized the encoding mode for HDMI
encoders to operate in HDMI mode only. This will not work properly when
connected to a DVI display. Solution: Video BIOS will now set the encoding mode when turning on the
device after determining which type of display is connected. This includes
the recommended mode for no device connected, which is DVI. |
GM965/PM985/GL960 G965/Q963/Q965 945GM |
|
|
N/A |
N/A |
N/A |
482800 |
Description: Set up
the build infrastructure for the first release of Bearlake-B. |
Bearlake-B |
|
|
Video
BIOS Build Date: 05/12/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1329 |
G965/Q963/Q965 |
|||||
|
1327 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1323 |
945GM |
|||||
|
1329 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
HSD 545378 |
N/A |
N/A |
472347 |
Description: A silicon bug promotes a system
hang after MI_FLUSH in the game “Beyond Good & Evil.” Solution: To
workaround the problem, a new "MT Constant Read Bug Fix Disable Chicken
Bit" is defined in Cache Mode Register 0. This new bit must be set to
"0" during Video POST. |
G965/Q963/Q965 |
|
|
86303 86738 |
1977491 |
N/A |
460377 |
Description: System does not boot up when
there are no output devices connected and “LVDS Configuration” in BMP is set
to “No LVDS.” The issue is encountered
because the default boot display device for mobile systems is LFP (in the
occurrence of no displays attached) and this created an infinite detection
sequence. Solution: In the event of no display devices
connected and “No LVDS” is set in the VBT, CRT will be used as the optional
default boot display device. |
915GM |
|
|
Video
BIOS Build Date: 05/05/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1327 |
G965/Q963/Q965 |
|||||
|
1327 |
GM965/PM985/GL960 |
|||||
|
1327 |
945G |
|||||
|
1323 |
945GM |
|||||
|
1327 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1327 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
HSD
545671 |
N/A |
N/A |
461703 |
Description: 1. Blank screen occurs on CRT while mode
switching to a VGA mode from CRT+EFP extended mode or from CRT+EFP clone
mode. This issue was root-caused as a silicon bug. 2. The mode switching sequence is not
completely following spec. The process for VGA plane disabling is not
performed properly. Solution: 1. Display/Overlay Planes
and Cursor Planes need to be off (as a workaround) right after pipe is
disabled in the mode switching sequence. 2. Verify the VGA plane is turned off
after the pipe is disabled, but before checking pipe (on/off) status. |
GM965/PM985/GL960 G965/Q963/Q965 |
|
|
N/A |
N/A |
N/A |
460840 |
Description: 1. Added new support for triggering the
display plane by re-writing Display A/B Surface Base Address Register. 2. Simplified Pipe Scalar assignment
algorithm. |
GM965/PM985/GL960 G965/Q963/Q965 |
|
|
576080 |
N/A |
N/A |
461151 |
Description: Integrated-LVDS is not
successfully enabled using the 1323 build. Solution: Updated the VBT to
the correct size; allowing VBIOS to use the correct panel information. |
GM965/PM985/GL960 |
|
|
N/A |
N/A |
952679 |
461352 461488 461491 |
Description: Currently the “Panel Color Depth”
setting (18bpp/24bpp) is part of the “General SDVO-LVDS” features in the VBT
and is used for initializing all panels. This restricts the customer from
configuring different panel entries with different panel color depths for a
single platform. Solution: Added the capability for setting
“Panel Color Depth” (18bpp/24bpp) for each panel entry for SDVO-LVDS in the
VBT. |
945G 915GM 915G |
|
|
Video
BIOS Build Date: 04/28/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1323 |
G965/Q963/Q965 |
|||||
|
1323 |
GM965/PM985/GL960 |
|||||
|
1315 |
945G |
|||||
|
1323 |
945GM |
|||||
|
1315 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1315 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
952679 |
459794 |
Description: Currently the Panel Color Depth
setting (18bit/24bit) is part of the General SDVO-LVDS features in the VBT which
will apply to all the panels. This restricts the customer from configuring
different panels with different Panel Color Depths on the same platform. Solution: The capability for setting Panel
Color Depth (18bpp/24bpp) for each panel has been added under SDVO LVDS
features in the VBT. |
G965/Q963/Q965 GM965/PM985/GL960 945GM |
|
|
576080 |
N/A |
N/A |
461151 |
Description: Screen lost when VGA mode
switching used DMU dos utility. Solution: Added workaround which will check
the power status of the monitor and enable DDBMunit
clockgating. Description: Text mode flickering problem for
TV output device. Solution: For improving the TV text mode
quality, the initial value for VGA data throttling override has been updated. |
GM965/PM985/GL960 |
|
|
Video
BIOS Build Date: 04/06/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1318 |
G965/Q963/Q965 |
|||||
|
1318 |
GM965/PM985/GL960 |
|||||
|
1315 |
945G |
|||||
|
1318 |
945GM |
|||||
|
1315 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1315 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
N/A |
460832 |
Description: The Chrontel
SDVO encoder CH7021 has a hardware bug. In the
event of some opcodes sent to the encoder, the encoder
will return a failure status of “Target Not Specified.” From the user point of view, this
would result in no video output. Solution: A workaround has been added to convert the error of “Target Not
Specified” as “SDVO Pending” for Chrontel CH7021 encoders
only. |
G965/Q963/Q965 GM965/PM985/GL960 945GM |
|
|
N/A |
N/A |
N/A |
460334 |
Description: Modified the BMP script file enabling the new BMP
feature allowing the user to modify the VBT data on BIOS.ROM image. Previously,
this could only be performed to the Video BIOS binary. |
945GM GM965/PM985/GL960 |
|
|
N/A |
N/A |
N/A |
460877 |
GM965/PM985/GL960
power on official release version. |
GM965/PM985/GL960 |
|
|
Video BIOS
Build Date: 03/29/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1315 |
G965/Q963/Q965 |
|||||
|
0329 |
GM965/PM985/GL960 |
|||||
|
1315 |
945G |
|||||
|
1315 |
945GM |
|||||
|
1315 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1315 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
N/A |
N/A |
Description: First GM965/PM985/GL960 Build. |
GM965/PM985/GL960 |
|
|
Video
BIOS Build Date: 03/27/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1315 |
G965/Q963/Q965 |
|||||
|
1315 |
945G |
|||||
|
1315 |
945GM |
|||||
|
1315 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1315 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
85001 |
N/A |
N/A |
459063 459739 459738 459737 |
Description: Video BIOS was not setting the VGA
2x bit when necessary. This resulted
in a small image on a display capable of twice the normal VGA timings. This capability should only be used when an
EFP does NOT support Native VGA timings and if it has a minimum X-resolution
of 1280. Solution: This fix will allow VGA modes to
be displayed at 2x for EFPs that do not support
native VGA timings and have 1280+ X-resolutions. |
G965/Q963/Q965 945GM 945G 915GM 915G |
|
|
Video
BIOS Build Date: 03/20/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1311 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1313 |
945GM |
|||||
|
1305 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
86303 86738 |
1977491 |
N/A |
460196 |
Description: System does not boot up when
there are no output devices connected and “LVDS Configuration” in BMP is set
to “No LVDS.” The issue is encountered
because the default boot display device for mobile systems is LFP (in the
occurrence of no displays attached) and this created an infinite detection
sequence. Solution: In the event of no display devices
connected and “No LVDS” is set in the VBT, CRT will be used as the optional
default boot display device. |
945GM |
|
|
Video BIOS
Build Date: 03/17/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1311 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1305 |
945GM |
|||||
|
1305 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
545040 |
N/A |
N/A |
549788 |
Description: There was a silicon bug consisting of an
ADD2-card detection failure for the A0 stepping. VBIOS previously had a
workaround to skip the ADD2-card detection for A0 support, but this silicon
bug has been fixed in G965 C0 silicon. Currently, VBIOS needs to support both
A0 and C0 silicon. Solution: Added Revision ID checking to
distinguish between A0 and C0 silicon. This workaround will skip ADD2Card
detection for G965 A0, but does not skip detection for G965 C0 silicon. |
G965/Q963/Q965 |
|
|
N/A |
N/A |
938545 |
459483 |
NEW
BMP OPTION “Allow Boot Display to DVI even if DVI is not attached” Description:
This allows the
system to boot to a DVI display even when it is not connected. Without a DVI
monitor connected, the standard vga timing of
640x480-60Hz will be used. This is only implemented when the associated BMP
setting is enabled. Note: For enabling this capability,
use the BMP utility and set “Allow boot display to DVI” to enabled. Also, EFP
should be selected in “VBIOS Boot Display Device” in the BIOS Setup Utility. |
G965/Q963/Q965 |
|
|
Video
BIOS Build Date: 03/10/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1305 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1305 |
945GM |
|||||
|
1305 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
83982 |
1971259 |
951317 |
459743 460150 |
Description: BMP Option “Integrated LVDS Channel Type” has
been added for each of the Integrated LVDS panel # profiles. This allows the
user to select: Automatic Selection, Single Channel or Dual Channel. The
Automatic Selection will execute the algorithm previously in place. This
option should be configured when LFP EDID Support is Enabled. BMP Note: There are a few options for implementing
this option correctly: either “Panel Type” in “LVDS Display Configuration”
must be set to the desired panel # OR the INT 15H 5F40 Hook must be enabled
and then the correct panel # selected in CMOS setup. |
G965/Q963/Q965 945GM 915GM |
|
|
83258 85668 |
1942257 |
N/A |
460159 |
Description:
Over a series of lid-switch events, there is a sporadic event of the system
locking up in a CRT detection sequence. Cause: The
Analog port was enabled when it should not be and the chipset would not
return a detection status. Solution:
The Video BIOS will disable the NOTE: This
change in detection may result in a “flicker” on a CRT with an active output. |
G965/Q963/Q965 945GM |
|
|
Video
BIOS Build Date: 03/03/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1302 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1302 |
945GM |
|||||
|
1302 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
545319 |
N/A |
N/A |
459336 |
Description: DVI display blanks randomly in a VGA mode
setting. Cause: Display DVO ports were not disabled/enabled
in the Set Mode function - following the Set Mode Sequence specified in G965 BSpec 1.0. Solution: Included the disabling/enabling of display
DVO ports in Set Mode function. |
G965/Q963/Q965 |
|
|
83982 |
1971259 |
N/A |
459505 459768 |
Description:
For a small number of LVDS panels, the algorithm determining Dual/Single
Channel for Integrated LVDS does NOT work properly. Note:
this algorithm is only executed when LVDS EDID is enabled in the VBT. Cause:
The algorithm has limited capability and will not necessarily work for all
panels. Since the various x and y
resolution combinations and dot clocks are defined, but with overlapping
values. Solution: To
aid this, a long-term solution is in process. The current modification made
to aid the current issue is to revert back to the algorithm used in version
1265. |
945GM 915GM |
|
|
Video
BIOS Build Date: 02/23/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1297 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1297 |
945GM |
|||||
|
1295 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
545430 |
N/A |
N/A |
459310 |
Description: System hangs when driver attempts
to program the second half of GTT table (reported in HSD sighting 545430.) Cause: VBIOS was programming the starting address
of the GTT table according to the aperture size which could be 256MB or
512MB. In the case of 256MB, the second half of the GTT table was actually
sitting beyond the Top of Stolen Memory. Solution: Always force GTT to a fixed size of 512KB;
regardless of the aperture size (256MB or 512MB.) |
G965/Q963/Q965 |
|
|
N/A |
N/A |
N/A |
459310 |
Description: CPU fault occurs in the Double Buffering test of vbetest.exe
with 640x480 16bit color mode after forcing GTT size to 512KB. Cause: A bug in the algorithm for display frame size. Due to this error, VESA
function 4F01h returned the wrong value for the Number of Image Pages. Solution: Corrected the algorithm for VESA function
4F01h. |
G965/Q963/Q965 945GM |
|
|
Video
BIOS Build Date: 02/17/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1295 |
G965/Q963/Q965 |
|||||
|
1295 |
945G |
|||||
|
1295 |
945GM |
|||||
|
1295 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1295 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
82069 |
1940882 |
N/A |
457779 458540 458541 458542 |
E-DDC Initialization: Video
BIOS has added an initialization sequence for E-DDC to execute if the
initialization for DDC2B is not successful.
This was added for a defect regarding an IBM monitor that did not
initialize from the old standard and would only accept the E-DDC
initialization sequence. A minor update was made for the
original G965/Q963/Q965/945GM builds with this change. See E-DDC specification for
details on this sequence. |
G965/Q963/Q965 945GM 945G 915GM 915G |
|
|
Video
BIOS Build Date: 02/09/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1290 |
G965/Q963/Q965 |
|||||
|
1290 |
945G |
|||||
|
1290 |
945GM |
|||||
|
1290 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1290 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
545436 |
N/A |
N/A |
458715 |
Workaround: this will disable
“Display A/B Trickle Feed” feature in order to fix a silicon issue which
resulted in display jitter during some 3D applications. |
G965/Q963/Q965 |
|
|
80853 |
1701914 |
N/A |
430363 435150 |
Issue: VBIOS did not convert DTD to
Intel DTD form correctly resulting with incorrect timings. This created corruption for 640x480 60 Hz
VESA modes with analog CRT on ADD2 cards. |
945G 915G |
|
|
N/A |
N/A |
N/A |
457718 457719 |
Change LVDS panel power cycle delay
time. This only affects T4 - the
panel’s power-up delay time; which is the minimum time from “PANEL POWER OFF”
to “PANEL POWER ON”. |
915GM 945GM |
|
|
77956 |
1940390 1962471 |
N/A |
458109 430315 |
VBIOS has
updated the architecture for DVI-I; implementing two structures during
initialization. Previously, one structure was used and either
configured for CRT or EFP (based on the attached display during POST.)
Also, a BMP option is now available for DVI-I (in Motherboard-Down devices.) |
G965/Q963/Q965 945GM 915GM |
|
|
84537 |
N/A |
948681 |
430301 |
HDMI Audio Support: Video
BIOS will initialize the ELD with Basic Audio Support for HDMI encoders and
update the status of the ELD_Valid and Presence_Detect bits depending on the power state of the
display. When VBIOS sets the display to the ON power state, these
bits will be set, otherwise, they will be cleared. This support is
mainly for the absence of the Gfx Driver when the
Audio Driver is present. |
G965/Q963/Q965 945GM |
|
|
82069 |
1940882 |
N/A |
457779 |
E-DDC Initialization: Video
BIOS has added an initialization sequence for E-DDC to execute if the
initialization for DDC2B is not successful.
This was added for a defect regarding an IBM monitor that did not
initialize from the old standard and would only accept the E-DDC
initialization sequence. See E-DDC specification for
details on this sequence. |
G965/Q963/Q965 945GM |
|
|
Video
BIOS Build Date: 01/25/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1281 |
G965/Q963/Q965 |
|||||
|
1284 |
945G |
|||||
|
1284 |
945GM |
|||||
|
1284 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1284 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
83716 |
N/A |
N/A |
458105 458107 |
Fixes an
issue regarding display switching via ACPI hot keys. Affects BMP: In the "General
Features", the "Display must be attached for CUI/Hot
Key" option is primarily for the hot-key functionality with the
driver. Previously, this option was also linked with the ACPI hot-key
option and then removed later. This release will once again link this
option to the ACPI hot-key functionality. |
945GM 915GM |
|
|
77956 |
1940390 1962471 |
N/A |
430314 430316 |
VBIOS has
updated the architecture for DVI-I; implementing two structures during
initialization. Previously, one structure was used and either configured
for CRT or EFP (based on the attached display during POST.) Also, a BMP
option is now available for DVI-I (in Motherboard-Down devices.) |
945G 915G |
|
|
Video
BIOS Build Date: 01/13/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1281 |
G965/Q963/Q965 |
|||||
|
1270 |
945G |
|||||
|
1281 |
945GM |
|||||
|
1270 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1270 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
545017 |
N/A |
N/A |
436620 |
1)
Added support for 5F21h SBIOS hook. 2)
Cleaned up code by rename the build
switches. No impact
on Binary. 3)
Added workaround to disable DDBMunit clock
gating to fix VGA mode switching issue in DMU DOS utility. |
G965/Q963/Q965 |
|
|
N/A |
N/A |
931176 |
436465 |
Add VBT bit
for Driver only feature. “CRT Hotplug/unplug Persistence on Restore Mode”. This has
no VBIOS code impact. |
945GM |
|
|
N/A |
N/A |
944575 |
436654 |
Support for 2048x1536 LVDS panel has been added. |
945GM |
|
|
83062 84577 |
N/A |
N/A |
436408 |
Removal of a previous WA for silicon issue regarding GTT for
945G, which not present in G965/Q963/Q965. |
G965/Q963/Q965 |
|
|
Video
BIOS Build Date: 01/06/2006 |
||||||
|
Build # |
Chipset Family |
|||||
|
1278 |
G965/Q963/Q965 |
|||||
|
1270 |
945G |
|||||
|
1270 |
945GM |
|||||
|
1270 |
915GM (Alviso) |
|||||
|
3394 |
|
|||||
|
1270 |
915G (Grantsdale) |
|||||
|
1252 |
865G ( |
|||||
|
1270 |
855GM (MGM) |
|||||
|
3364 |
845G (Brookdale) |
|||||
|
3361 |
830M |
|||||
|
Video
BIOS Changes Since Last Build |
||||||
|
Sighting# |
Bug# |
RCR# |
DCN# |
Description/Issue fixed |
Chipset Family Affected |
|
|
N/A |
N/A |
931176 |
436465 |
Add VBT
bit for Driver only feature. “CRT Hotplug/unplug Persistence on Restore Mode”. This has
no VBIOS code impact. |
G965/Q963/Q965 |
|
|
83560 |
N/A |
N/A |
447384 |
Issue: 1) SDVO LVDS support for 10x7 and
14x10 panels. 2) Display out of sync for TV. Resolution: Handle display polarity
correctly for SDVO port. |
G965/Q963/Q965 |
|
|
83559 |
N/A |
N/A |
457711 |
Issue: Fixed DFP losing sync issue for
ELPIN tests. Resolution: Solved SDVO port
Enabling problem. |
G965/Q963/Q965 |
|